Typically, silicon wafers for solar cells are 156 mm×156 mm and 180 to 200 microns thick. Because the highly refined silicon used to make these wafers is quite expensive, it would be advantageous to use thinner wafers, in order to reduce materials costs. Further, with an appropriate cell construction, the relatively thinner silicon wafers have relatively higher efficiency than thicker silicon cells. Cell constructions that would show higher efficiency using thinner wafers are those that result in low surface recombination and good light trapping. The PERC cell structure is currently the most widely adopted such cell structure. (PERC stands for Passivated Emitter Rear Contact.) The reason for this higher efficiency is thought to be lower volume recombination due to shorter distance in a thinner body than a thicker one, to the collecting pn-junction. The amount of increase in cell efficiency resulting from thinner thickness depends on the cell construction or architecture, and also on the electronic quality of the wafer. Generally, greater increases are associated with lower wafer electronic quality. Thus, there is a strong motivation to use thinner wafers, both for reduced wafer cost and for increased cell efficiency. A further advantage of thinner wafers is that the minority carrier injection level is higher per unit volume because the same number of photons are absorbed in less material for a higher injection level, and multi-crystalline silicon material has higher bulk minority carrier lifetime at higher injection levels.
Silicon wafers for photovoltaics (PV) are typically made by growing or casting an ingot and then by slicing the ingot into wafers, typically by wire sawing. Wire sawing can be used to produce wafers thinner than the standard 180-200 micron thickness. However, such thinner wafers have been found to break during cell fabrication, electrical interconnection and encapsulation into a module. For these reasons, after trying thinner wafers (as thin as 120 microns), the industry has returned to the previous standard of 180-200 microns. For typical cell structures including PERC using multi-crystalline silicon material, making wafers thinner than 80 microns does not provide any further appreciable efficiency gain.
The increased breakage of thinner wafers has several origins. During cell fabrication, wafers often break by propagation of a defect from an edge of the wafer. Edge defects include cracks and thin spots. Further, during handling, new cracks and defects are created at the edges, because they are the locations of contact with other pieces of equipment during the manufacturing process. Cracks starting from an edge are a problem during cell making and module fabrication. In general, it has been found that with presently used machinery and methods, PV wafers that are thinner than 150 microns are damaged with unacceptable frequency to be practical.
In addition, bus wires and other electrical connections must be attached to the top and bottom electrodes of cells to interconnect them. These wires can be fairly substantial in cross section to be able to carry the large currents generated by a solar cell. For example, a typical copper bus wire in a 3-buswire cell can be 1.6 mm wide and 0.15 mm thick. These wires are attached to the metallization on a cell by soldering or using conductive adhesive. The attachment itself creates stress between the wire and the metallization, especially in the case of soldering. The coefficients of thermal expansion of the wire and the silicon cell are different (the wire's being higher than the silicon's) and therefore changes in temperature lead to more stresses between wire and cell. The attachment and thermal expansion stresses can cause delamination of the wire and/or metallization from the cell, especially near the edges of a cell. Further, the bus wires must be bent down from the top surface of the cell to wrap under to the back surface of the adjacent cell. This bent wire adds to delamination stresses at the metallization near the edge of the cell. Further, if improperly bent, the wire can actually touch the edge of the cell, thereby causing or propagating edge cracks.
According to another method of fabrication, a semiconductor wafer is formed from a semiconductor melt, generally using techniques disclosed in U.S. Pat. No. 8,293,009, issued on Oct. 23, 2012, entitled METHODS FOR EFFICIENTLY MAKING THIN SEMICONDUCTOR BODIES FROM MOLTEN MATERIAL FOR SOLAR CELLS AND THE LIKE, by Sachs, et al., which is fully incorporated herein by reference). The technology disclosed in this patent is referred to herein generally as Direct Wafer® (DW) wafer forming technology. According to this technology, a thin semi-conductor body, such as a wafer, is formed from a melt of semi-conductor material, rather than being sawn from an ingot, or grown between strings, or some other method.
Briefly, according to the Direct Wafer (DW) wafer forming technology, a pressure differential is applied across a porous mold sheet and a semiconductor (e.g. silicon) wafer is formed thereon. Relaxation of the pressure differential allows release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted through the thickness of the forming wafer. The liquid and solid interface is substantially parallel to the mold sheet. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The porous mold sheet must be sufficiently permeable to allow flow of gas through it. It must not be so permeable as to allow the intrusion of molten material into the openings of the porosities during the time the pressure differential is provided. Otherwise, the porosities would become clogged and the pressure differential could not be maintained. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means. The pressure differential, sometimes referred to in the Direct Wafer technology patent and herein as the differential pressure regime, may be established by maintaining the melt surface at atmospheric pressure, and maintaining the back surface of the mold sheet at less than atmospheric pressure. In another embodiment differential pressure between the faces of the mold sheet is generated by venting the back face of the mold sheet directly to atmosphere, while maintaining the atmosphere on the forming face of the mold sheet at a pressure substantially higher than local atmospheric pressure. An advantage of this embodiment is that a vacuum pump is not required. The mold face and the melt surface contact each other for a period of time that may be referred to as a contact duration. During at least a part of the contact duration, the differential pressure regime is provided. It is beneficial to form the wafer from the melt, and it is considered an invention of the Direct Wafer technology patent, and also one of the inventions disclosed herein, to create a solidified body within the melt, and to form such a body, for instance a wafer, on the mold sheet (or, in the case of inventions disclosed herein, a template). It need not be released from the mold sheet (or template) to constitute a valuable article of manufacture. But also, the formed wafer can be removed from the mold sheet in a variety of ways. In some cases, the differential pressure regime can be removed, i.e., if a vacuum is used, it can be turned off, and the wafer falls off. Or, the differential pressure regime can be reduced—i.e., the degree of vacuum can be reduced, or, the difference in pressure can be reduced. Further, mechanical means, such as stripping pins, a stripping frame, or other tools that mechanically contact the wafer and press it away from the mold-sheet, can be used.
Regarding the porosity of the mold sheet, in one embodiment, the porosity of the surface touching the at first molten and later solidified, semiconductor material, must be small enough in scale so as to make it difficult for the molten semiconductor to enter into the porosities. Typically, the pore size of interest may range from 0.1 to 10.0 microns. The porosities are interconnected so that gas passing through the porous medium of the mold typically flows in complex patterns, thus accommodating local blockages by finding circuitous paths around any blockages.
The very outer surface of the porous body, which forms the surface that faces and contacts the surface of the molten material, may be slightly non-planar (on a microscopic or slightly larger scale), thus allowing the molten semiconductor to touch the mold surface only at particular, although numerous and densely packed locations. With this structure, gas can flow a bit laterally between the molten material and the surface of the porous mold. This permits the suction that is provided by the differential pressure regime to apply force upon the wafer surface over a very large percentage of its surface area, approximately 100%. This is in contrast to a case where a smaller number of larger holes could be provided, through which holes the differential pressure could be provided, to establish an equivalent pressure differential. In the latter case, the locus of the pressure differential is confined to the relatively small surface area of the relatively small number of large holes In contrast, in the former case, of a truly porous body, because the gas can flow laterally, the pressure differential is actually present in a much more distributed nature over the entire surface area of the mold and attached wafer. The word porous is used herein to describe the former case, and not the latter.
Wafers made by a Direct Wafer (DW) wafer forming technology method have certain advantages over wire-sawn wafers, for instance there is much less waste of raw silicon, because there is no material ground to powder and thus lost to sawing. Furthermore, the method by which they are made, principally by contacting a mold to a surface of molten material, lends itself to specific control of certain aspects of wafer fabrication, as discussed below. However, like wire-sawn wafers, wafers made by the Direct Wafer patent technology method of the standard thickness are also less efficient than would be thinner wafers made by the same technique, for the same reasons of efficiency discussed above. Further relatively thinner wafers made by Direct Wafer patent technology are more fragile or otherwise not as strong as standard thickness, relatively thicker wafers made by the same Direct Wafer patent technology. Furthermore, relatively thinner wafers made by Direct Wafer patent technology methods would use less raw semi-conductor material than would relatively thicker wafers made using Direct Wafer patent technology.
Thus, it would be desirable to reduce the costs of PV modules, and, in particular, to reduce the volume and thus the cost of silicon required for each wafer, manufactured by whatever method, without sacrificing strength, durability, or performance. It would also be desirable to increase the strength of fabricated wafers, without unduly increasing their cost, weight, size, rigidity, or other properties. It would also be desirable to provide wafers having a relatively higher efficiency than wafers of the standard 180-200 micron thickness. It would also be desirable to enable making electrical connections to generally thin semi-conductor wafers, to be able to connect them to each other and to other components.
Researchers have experimented with powder based technologies and settering, to create wafers that have some regions that are thinner than others, for instance with a thinner interior and a thicker perimeter. See for instance U.S. Pat. No. 7,456,084 B2, in the names of Jonczyk et al., METHOD OF USING A SETTER HAVING A RECESS IN MANUFACTURING A NET-SHAPE SEMICONDUCTOR WAFER (the '084 patent). In this settering work, powdered silicon is provided in a mold (referred to as a setter in the '084 patent) of the desired shape, and it is heated, causing the powder material to melt and coalesce into a solid body of multi-crystalline silicon. A major difficulty with the technology disclosed in the '084 patent, and with any powder technology, is that the interstitial oxygen content is unacceptably high for a semi-conductor, particularly for photovoltaic use. This is because, without conducting extraordinary steps, native oxide on the powder particles results in high interstitial oxygen levels in the wafers. Relatively smaller particles result in relatively more interstitial oxygen in the finished product. To achieve relatively thinner wafers, relatively smaller particles must be used. Thus, to achieve relatively thinner wafers, relatively more interstitial oxygen will be present in the wafers, if made from particles.
For instance, the '084 patent discusses wafers having a range of relatively large thickness, between 300 and 1000 microns, made from powder. Based on theoretical analysis conducted by the present inventors, it is believed that this would have resulted in wafers having interstitial oxygen content of between 6×1017 and 2×1018 atoms/cc, as measured by Fourier Transform Infrared Spectroscopy (FTIR), method ASTM-F1188. As a theoretical example, assuming spherical 150 micron diameter powder with a 1 nm thick native oxide shell a total oxygen concentration of 1×1018 atoms/cc would be present. In practice, silicon powder is non-spherical with aspect ratio >2:1, so they will contain greater surface area to volume ratio the theoretical spheres used in the estimate above, and even higher oxygen concentration. To achieve thinner wafers, having thickness of less than 300 microns, smaller particles would be required, resulting in higher oxygen concentration. It should be emphasized that, although the '084 patent mentions theoretically a wafer as thin as 100 microns, the '084 patent states that more typical would be 350-900 microns. Most importantly, it does not have any formal examples, nor does it discuss having made any actual wafers according to the processes disclosed therein. The only wafers that it discusses as having thicker and thinner regions are 900 microns thick at their thinner portions, and there is no explicit discussion of such wafers having been made.
In general, it is believed that particles to be used to fabricate thin wafers should be no larger than ⅓ the finished thickness of the wafer. For instance, to make a wafer thinner than 150 microns, the powder particles should be smaller than 50 microns. Particles of such small dimensions would have a very large surface area relative to the volume of material provided. This relatively large surface area is accompanied necessarily by a relatively large amount of interstitial oxygen, through native oxide, hydrocarbons and metals. Too much interstitial oxygen would likely lead, not only to poor performance, but in the extreme, may prevent the powder from properly melting and crystallizing. Oxygen on such small powder would also form massive amounts of SiO, which could condense anywhere in the furnace where the temperature is even a little lower than the melt temperature.
It is acknowledged in the '084 patent, at col. 5, lines 1-10, that the presence of silicon oxide in the semi-conductor material (or other oxides for other semi-conductors) is an undesirable contamination, and that it is relatively worse for relatively smaller particle sizes. Thus, the lower limit of particle size, which limits the thinness that can be achieved in the final wafer, is limited by the potential for interstitial oxide contamination. To have used 50 micron particle size powder, as would be required to fabricate 150 micron or less thick wafers, would result in nearly four times as much oxygen on the smaller particles of powder as would have been present on particles used to make 300-600 micron wafers. Thus, to have used 50 micron particles (to achieve a 150 micron thick wafer) it would be expected to have resulted in a wafer having at least 3×1018 atoms/cc interstitial oxygen, and most likely more.
It would be desirable to have interstitial oxygen levels at any value below 6×1017 atoms/cc and preferably less than 2×1017 atoms/cc. Achieving each degree of a lesser amount of interstitial oxygen (e.g., 5×1017 atoms/cc, 4×1017 atoms/cc, etc., just to pick two break points, provides relatively more advantage than higher amounts.
It is theoretically possible through known heat-treating, such as a gettering, to precipitate interstitial oxygen above approximately 2×1017 atoms/cc. Thus, the interstitial oxygen reduces to possibly approximately that value, but the total oxygen in the crystal remains relatively and detrimentally high, at at least 8.75×1017 atoms/cc (=10 ppmw), as measured by an IGA (Interstitial Gas Analysis) method, such as is provided by LECO corporation of St. Joseph, Mich. However, it would be desirable to have total oxygen levels at less than 8.74×1017 atoms/cc. Any value below this value, and preferably bless than 5.25×1017 atoms/cc (=6 ppmw) would provide advantages. Achieving each degree of a lesser amount of total oxygen (e.g., 7×1017 atoms/cc, 6×1017 atoms/cc, just to pick two break points, provides relatively more advantage.
Another problem related to powder based wafer forming, particularly with semi-conductors such as silicon, is due to silicon's very high surface tension. A thin wafer cannot be made from powder and setter technology if all of the silicon is melted in any location at the same time. A certain minimum amount of un-melted silicon is required to break surface tension. Otherwise, balls of silicon form, rather than flattened thin structures. The wafer making process disclosed in the '084 patent involved melting the silicon powder partially, and then crystallizing it on one side, before melting the remaining un-melted powder from the other side and continuing growth epitaxially on the previously grown silicon. See generally col. 7, lines 55-col. 8, line 64, and FIG. 1 and FIG. 2. The text describes a top-down heating and grain growth process. FIG. 2 of the '084 patent shows heat being applied from the top and bottom of the melting and then solidifying body and FIG. 12 of that patent, col. 15 lines 4-19, showing the same, as well as partially melted material 89, atop still particulate material (no reference numeral). Such a process is very difficult with very thin powder bed thickness. Melting the full depth of the silicon powder at any one location must be avoided everywhere. Otherwise, the thin layer of molten material will ball up, leaving holes to form adjacent the region of balling. Thus, using a powder and setter technology, it is difficult if not impossible to obtain wafers of thinner than 200 microns, with silicon (and any other semi-conductor with similarly high surface tension) because it is very difficult to melt only a portion of the depth of such a shallow body of powder particles, without melting all of the rest of its depth at one time, which would result in the balling up of that region of molten semi-conductor.
Fabricating a wafer from powder particles also presents another problem related to large thickness steps from one location to another, which problem is due to the fact that powder is at most 50% dense, and more typically 33% dense. Due to this problem, it is not possible to have a region more than 20%-30% thicker than an adjacent location without having a gross lack of flatness on the opposite face of the formed body and a markedly thin portion at the transition between the thicker and relatively thinner regions. (Stated differently, the ratio of thicknesses of adjacent regions cannot be greater than 1.3:1, or maybe even as small as 1.2:1, depending on the particle sizes, required part quality and dimensional uniformity.) The density of powder is about ⅓ the density of solidified material. (The particle size has some effect on this fraction.) The setter apparatus is illustrated with respect to FIGS. 9 and 12 of the '084 patent. If a recess 73 in a setter 70 is to be used to form a perimeter in the finished product, that is raised above a thinner interior region, formed at the region 74 of the setter, both the recess 73 and the shallower region 74 must initially be provided with enough depth/volume of particles to create the finished product.
Consider what would happen for the following set up. If a recess 74 in a setter were 100 microns deep and the wafer thickness was desired to be 300 microns thick in the main, interior region, then, for the main region, it would be necessary to pile powder above this region to a depth of three times the final 300 micron thickness, for a total of 900 microns. This would mean that above the trench, the thickness would be 1000 microns. After melting, the thickness of the finished body would be approximately ⅓ the depth of the powder that was above it. Thus, in the interior region, it would be 300 microns thick. Above the trench, it would be ⅓×1000 microns=333 microns thick. But, the trench is 100 microns deeper than the interior. Thus, thickness of the perimeter would be 333 microns as measured from the bottom of the trench, 100 microns below the center region, and the thickness of the interior would be 300 microns, measured from the flat interior region. The back surface of the formed body would be far from flat, because the opposite surfaces would be offset by the 100 microns of the trench. The distance to the back surface above the trench from the bottom of the trench would be 333 microns. The distance from the level of the bottom of the trench to the back surface above the interior region would be 400 microns, because the thickness above the interior region is 300 microns, and the interior region is spaced 100 microns away from the bottom of the 100 micron deep trench. Thus, adjacent regions of the back surface at the interface between the perimeter above the trench and the region above the interior will be at different distances from the bottom of the trench of 333 microns and 400 microns, respectively, leaving a jog of 67 microns between the two.
Due to the lack of flatness, there will be a thinner portion adjacent the corner between the trench and the interior region. This thinner portion could be weaker, or constitute a stress raiser, and is generally undesirable. The lack of flatness is worse for deeper trenches, provided to establish larger extensions around the perimeter. This is because the difference due to the added extension would be present in the absolute, to the same degree as the increased extension, but the added powder due to this added extension would compress to ⅓ the added amount. Thus, for a perimeter trench that is 200 microns deep, the jog at the back surface would be a difference of 124 microns (=300−((1100 microns/3)−200).
The foregoing considerations can also be expressed in terms of the ratio of the size of the raised, extended portion of the thicker region, as compared to the thickness of the thinner region. If the surface of the thinner region is considered a base level, then with the settering method, it is typically not possible to fabricate a body with a raised portion that extends beyond the base level surface to such a degree that the ratio of the raised portion extension above the base level to the thickness of the thinner region is larger than 0.11. In any case, the '084 patent does not disclose any examples of bodies with larger ratios. The only example disclosed therein has a thin region of 900 microns, with a raised portion at most 100 microns, resulting in a ratio of 100/900=0.11.
Thus, an object of an invention hereof is a semi-conductor wafer that is thinner, in certain controlled regions, than a standard 180-200 micron thick semi-conductor wafer, as thin in significantly large portions as 80 microns, and even in some cases as thin as 50-60 microns, but which thinner wafer is strong and robust enough to be used in conventional, or nearly conventional photovoltaic applications. Another object of an invention hereof is a semi-conductor wafer that has relatively less semi-conductor in its volume than a standard semiconductor wafer of the same surface area. Still another object of an invention hereof is a method of making such a locally thinner, but still strong wafer. Yet another object of an invention hereof is a method of making such a lower volume semi-conductor wafer. Yet another object of inventions hereof is to create wafers with three-dimensional geometry. A further object of inventions hereof is to create such thin wafers with acceptable interstitial oxygen content, for instance at any value less than 6×1017 atoms/cc, and preferably less than 2×1017 atoms/cc. A related object is to create such wafers with total oxygen of any value less than 8.75×1017 atoms/cc (=10 ppmw) and preferably less than 5.25×1017 atoms/cc (=6 ppmw) as measured by IGA. Yet another object is a semiconductor wafer that has regions of different thicknesses, where adjacent regions have a thickness ratio of greater than 1.28:1. A related object to the foregoing is a semiconductor wafer that has regions of different thicknesses, where the extension of the thicker region above the base level of the thinner region is greater than 0.11 times the thickness of the thinner region. Still another object of an invention hereof is a semi-conductor wafer that has a regions of different thicknesses, where the thinner region is preferably thinner than 180 microns and in a specific embodiment, extends over at least 80% of the surface area and as much as 95% of the surface area.